1. Technical Field
The present invention relates to semiconductor device packages and, more particularly, to a stacked-type semiconductor device package.
2. Description of the Related Art
In the semiconductor industry, packaging technologies for integrated circuits (ICs) have been advancing to meet requirements for miniaturization and mounting reliability. For example, the requirement for miniaturization results in acceleration of technological development for a package having a similar size in relation to a semiconductor chip. Further, the requirement for mounting reliability places importance on packaging technologies that are capable of enhancing efficiency of a mounting process and improving mechanical and electrical reliability after the mounting process is completed.
Including requirements for multi-functionalization as well as miniaturization of electric and electronic appliances, various technologies have been studied and developed to provide high-capacity semiconductor products. Methods for providing the high-capacity semiconductor products include increasing the capacity of a memory chip, i.e., increased integration of the memory chip. The increased integration of the memory chip may be achieved by integrating more cells into a limited space of the semiconductor chip.
However, the increased integration of the memory chip requires high-level technology such as precise ultra-small linewidth processes as well as significant development time. Accordingly, stacking technologies have been proposed as alternative methods for providing high-capacity semiconductor products.
In recent years, demands for system-in-package (SIP) and multi-chip package (MCP) technologies have been rapidly increasing for applications in mobile appliances. The SIP is a special form of the MCP where different semiconductor devices (e.g., DRAM, SRAM, CPU, etc.) are integrated into one package. In the SIP and the MCP, even when only one semiconductor device is defective, the package is treated as a bad package although the other semiconductor devices in the package are not defective. Therefore, it is difficult to improve production yield of these types of packages.
In order to overcome these problems, a package on package (POP) or a package in package (PIP) technology has been used. In the POP and PIP technologies, after semiconductor chips are assembled into a semiconductor chip package, good semiconductor chip packages are selected by means of a test process so that they can be manufactured into one package. However, a conventional POP needs solder balls provided on a bottom surface of respective semiconductor chip packages to stack and electrically connect the semiconductor chip packages. The solder balls lead to an increase in thickness of the package manufactured by means of a PIP method. Moreover, since a space is needed between the semiconductor chip packages, a thickness of the package increases with an increase in the number of stacked semiconductor chip packages.
In addition, a process becomes complex when semiconductor chip packages having different structures or sizes are stacked by means of a POP method using solder balls. The present invention addresses these and other disadvantages of the conventional art.